1. Field of the Invention
This invention relates to a tightly coupled multiprocessor system and, more particularly, to a system which can distribute I/O interrupts to processors according to load conditions of the processors without converging them to one of the processors.
Recent improvements in hardware techniques have promoted practical use of a tightly coupled multiprocessor workstation having a number of processors. It is desirable that a workstation of this type provides various flexible I/O functions in addition to a high-speed arithmetical computing function.
Most conventional systems have a configuration in which each I/O device is locally connected to each processor or an alternative configuration in which a specific processor has a centralized control over I/O devices (for example, JA PUPA 63-147252). These systems are based on such a premise that each I/O is controlled by a particular processor. Therefore, although they are readily realized, load distribution of I/O processing is almost impossible, and it is difficult efficiently to present users high-level I/O functions.
On the other hand, such an expedient is explored that load distribution of I/O processing is performed on a tightly coupled multiprocessor system. In order to realize load distribution of I/O processing, it is essential that all processors in the system can operate the I/O devices equally and directly. In particular, it is necessary to realize the function of distributing interrupts from the I/O devices to the processors. For distribution of interrupts, however, the arbitration of an interrupt is necessary so that two or more processors do not accept a single interrupt concurrently. Unless the interrupt arbitration is realized, a request from a single I/O device will be processed redundantly. It is also important for realization of I/O load distribution that an interrupt be transmitted to a processor that currently executes a least-loaded job or a low priority job.
Systems effecting load distribution of I/O processing are disclosed in "The Design and Development of a Very High Speed System Bus--The Encore Multimax Nanobus", D.J. Schanin, Proceedings of Fall Joint Computer Conference, pp. 410-418, November 1986, and in "Balance: A Shared Memory Multiprocessor System", S.S. Thakkar, P. Gifford, G. Fielland, Proceedings of 2nd International Conference on Supercomputing, pp. 93-101, May 1987.
These two systems are equipped with a function for arbitrating interrupts. These two systems effect interrupt arbitration by using, as a index, the priority of a process currently executed by each processor or the number of pending interrupts existing in the interruption queue and then achieves I/O load distribution. However, there still remains a possibility that two or more processors win the arbitration. In this case, one of the processors that should accept the interrupt is finally selected by means of a specific slot number of the processor.
These two expedients for interrupt arbitration, however, cannot realize satisfactory I/O load distribution because interrupts are always sent to a processor determined by the slot number indicating the physical location thereof if all processors are executing processes in the same priority level. In addition, when interrupt queues of all processors are empty, interrupts are always sent to a specific processor even if it currently executes an important job. Further, it is absolutely impossible, or possible only upon start of the system, to designate a group of processors that accept interrupts in each interrupt level. Therefore, these systems cannot dynamically designate or change a group of processors that accept interrupts during operation of the system according to the load conditions of the processors.
Further, no existing system is equipped with hardware for control of interrupt arbitration only in processors. Existing systems add control logic circuitry not only to processors but also to I/O devices, or alternatively, newly provide a specific I/O device with communication lines added to the system for interrupt arbitration. Therefore, the scale of the control hardware for realizing interrupt arbitration cannot be disregarded. There are various methods for realizing arbitration such as repeated message communication, an asynchronous back-off method, but it is not expected that they arbitrate interrupts and transmit the result to a processor in a short time.
Other prior art techniques related to the present invention are JA PUPA 61-87448, JA PUPA 62-187955, and JA PUPA 1-279354. JA PUPA 61-87448 discloses changing priorities for bus arbitration every time when bus arbitration is carried out. JA PUPA 62-187955 discloses changing priorities for bus arbitration cyclically every time when bus arbitration is carried out. JA PUPA 1-279354 discloses changing priorities for bus arbitration cyclically every time when bus arbitration is carried out, and setting upper and lower limits for each processor, and further changing the priority of each processor between the upper and lower limits. In this case, if the upper and lower limits of a given processor are set equal, its priority can be fixed at the value. All these prior art techniques, however, are directed to arbitration of bus requests, and does not teach either distributing a load by interruption in first arbitration or eliminating convergency of interrupts in additional second arbitration.